1. Field of the Invention
The present invention relates to a memory and operating method thereof. More particularly, the present invention relates to a P-channel non-volatile memory and operating method thereof.
2. Description of the Related Art
Electrically erasable programmable read-only-memory (EEPROM) is a type of non-volatile memory that allows multiple data entry, reading and erasing operations. The stored data will be retained even after power to the device is removed. Moreover, the access speed is fast, the storage capacity per unit weight is large and the access device occupies only a small volume. With these advantages, EEPROM has become one of the most widely adopted non-volatile memories for personal computer and electronic equipment.
A typical EEPROM has a floating gate and a control gate fabricated using doped polysilicon. To prevent a conventional EEPROM from over-erasing in an erasing operation and leading to the registering of erroneous data, an additional select gate fabricated using doped polysilicon is disposed on the sidewall of the control gate and the floating gate above the substrate. In other words, a select transistor is set up on one side beside the sidewalls of the control gate and the floating gate.
In the conventional technique, a charge trapping layer is sometimes used to replace the polysilicon floating gate. The charge trapping layer is fabricated using silicon nitride, for example. In general, the silicon nitride layer is sandwiched between an upper and a lower silicon oxide layer to form an oxide-nitride-oxide (ONO) composite layer. This type of device is often referred to as a silicon/silicon oxide/silicon nitride/silicon oxide/silicon (SONOS) device.
However, most SONOS memory devices are N-channel non-volatile memories. The N-channel non-volatile memory has small channel current and poor energy utilization. There is only 1 electron injection for the passage of a total of between 108˜1010 electrons. Therefore, in a low energy consumption portable electronic product area, the applications of an N-channel non-volatile memory is rather restricted. If the memory cell further incorporates a select transistor, the dimension of the device will increase and accordingly limit the development of a higher level of integration for the devices.